Intel has updated its high-end Itanium 2 product line and outlined future products.

As we reported previously, the new products - originally codenamed Madison - sport larger cache sizes which, said Intel marketing manager Adam Martin, offer performance increases of up to 25 per cent over the existing 1.5GHz Itanium 2 with 6MB L3 cache. Clock speeds are slightly higher.

The six new products fall into three categories: performance, two-way, and low-power. In the performance range, the three new processors are multi-way capable, consume 130 Watts of power and are available in the following configurations:

  • Clock speed of 1.60GHz with 9MB of L3 cache
  • Clock speed of 1.6GHz with 6MB of L3 cache
  • Clock speed of 1.5GHz with 4MB of L3 cache

Designed for demanding enterprise-level applications such as transaction processing, users could expect 40 per cent better price/performance than equivalent RISC-based systems, claimed Martin.

Two-way systems are catered for by two 99 Watt products (Fanwood):

  • Clock speed of 1.6GHz with 6MB of L3 cache
  • Clock speed of 1.5GHz with 4MB of L3 cache

Aimed at clustered applications, said Martin, they provide 50 per cent better price/performance than equivalent RISC-based systems.

Meanwhile, the low-power, 62 Watt version (Millington) is clocked at 1.3GHz and houses a 3MB L3 cache. Designers of blade and other high-density systems are likely to choose this chip which, claimed Martin, offers a 40 per cent performance increase over Intel's existing 1GHz part while allowing itself to be powered down when not required.

Montecito, the next CPU iteration, will be in the second half of next year, said Martin. It will be the first dual core Itanium, with cache sizes up to 24MB plus "other improvements at the platform level", such as multi-threading, and others designed to boost specific applications such as transaction processing. It will offer from one-and-a-half to two times the performance.

Specifically, Montecito will offer four times the number of threads, better reliability through a cache-correction technology codenamed Pellston and "more robust virtualisation" - another codenamed technology, Silvervale, provides this, though details remain vague.

Other energy-saving designs will allow the chip to reduce its power consumption by up to 60 Watts. "You might want to do this overnight", suggested Martin. He said that clock speeds will go up but although he could not be specific, though he said that they would "give a pretty significant performance increase - up to 70 per cent."

Martin described Montecito as "a very healthy product that's being sampled to customers as we speak. Montecito is dual-core so we want to make sure everything else is fitting around it. We need HP, SGI and IBM to have their platforms ready."

After Montecito comes Tukwila in 2007, using technology borrowed from the now-defunct Compaq Alpha project, as reported here. It will be multi-core but Martin could not say how many cores would be incorporated. "The die is much smaller than Xeon," he said.

"We are developing a common platform architecture between Xeon and Itaniums, which with four-way systems and up will cut the cost of Itanium platform. For system manufacturers, a common platform makes it cheaper to build," said Martin. He added that all the upcoming products are socket-compatible with existing systems, helping to cut the cost of system production.

What's remarkable about this announcement is Intel's de-emphasis of clock speeds coupled to performance. Instead, Intel clearly plans to plough on with adding features rather than Hertz in order to generate more performance from its silicon.