Researchers at Intel claim to have found a better way to insulate circuits, enabling them to save energy as they pack more transistors onto each processor.
Intel could start building chips with these new "tri-gate transistors" by 2010, enabling either a 45 percent increase in speed or a 35 percent reduction in total power used, compared to the company's current 65-nanometer process transistors, said Mike Mayberry, director of components research and vice president of Intel's Technology and Manufacturing Group.
Chip efficiency has become a powerful markerting tool. AMD claims its Opteron chip will reduce electricity costs compared to Intel's Xeon chips. And Sun Microsystems frequently taunts competitors HP and IBM for using fans to cool their servers, instead of using more efficient chips like Sun's UltraSPARC T1.
Intel's new technology would also extend the reach of Moore's Law, the prediction made 40 years ago by Intel co-founder Gordon Moore that the number of transistors on a chip would double about every two years.
Engineers have recently predicted that trend would soon end, because electricity tends to leak out of tiny wires as chip geometry shrinks below 90 nanometers.
One solution is to build chips with multiple cores that run at slower speeds, since chips leak more electricity and run less efficiently as they run faster than 2GHz. Chip makers from Intel to AMD and Sun have all followed this path.
Another answer could be carbon nanotubes, according to scientists at IBM, who said in March they had built an electronic integrated circuit by combining conventional silicon technology with a carbon nanotube molecule.
But Intel says its tri-gate solution is the best.
"Compared to carbon nanotubes, it is far easier to build," Mayberry said. "The problem with carbon nanotubes is that no one knows how to put them in a particular spot except by moving them one at a time. Even our smallest chips have millions of transistors, so that is an insurmountable challenge."
A tri-gate transistor is a component in the standard CMOS (complementary metal oxide semiconductor) design, but acts as a better "traffic cop" to control the flow of electrons, surrounding each wire on three sides instead of just one.
"It's better to wrap the gate around, just like it's easier to block a garden hose by squeezing on all sides than just holding your thumb on one side," he said.
The technology is still on the drawing board, but Intel designers will be able to quickly apply it to new chips someday because they can use existing equipment in the fabrication plants.
"This will be an option for chips somewhere beyond 45 nm - in the 32 or 22 nm mode - so that gives us confidence we can continue scaling Moore's Law into the next decade," said Mayberry.
Intel has said it will be making more chips with 65-nm geometry than 90 nm by the third quarter of 2006, and move to 45-nm in 2007 and 32-nm by 2009.