IBM and AMD have developed new strained silicon technology that they claim will increase chip performance by a quarter.
The new manufacturing technique, which the companies are calling Dual Stress Liner, will help improve performance on chips from both companies starting early next year. IBM and AMD claim they are the first to show simultaneous performance improvements on both positive and negative transistors using conventional materials.
As it has become more difficult for chip companies to improve transistor performance by simply shrinking transistors, they have turned to alternative techniques. Strained silicon is a technique in which a lattice pattern of silicon atoms is either stretched or compressed to improve the speed at which electrons flow through the silicon. Positive transistors run faster when they are compressed, and negative transistors run faster when they are stretched.
The companies believe that by using their strained silicon techniques on both positive and negative transistors they can improve transistor speed by as much as 24 percent. The new technology will be integrated into AMD's Opteron and Athlon 64 processors and IBM's Power processors in the first half of next year.
In 2003, AMD and IBM agreed to work on techniques for advanced transistor manufacturing. Joint development teams now work at both their lead manufacturing facilities. The companies recently extended that agreement to carry through 2008.
Researchers from both companies will present a paper outlining their technique at the International Electron Devices Meeting (IEDM) in San Francisco later today.