The "tera" era of the computing world is approaching, warns Intel's CTO Pat Gelsinger, and the semiconductor industry is going to have to rethink many of the architectural approaches it has taken to build today's processors.
In his keynote at Intel's Developer Forum in San Francisco, Gelsinger explained that the vast datasets of the future will require an overhaul of existing chip technology.
Gelsinger traditionally takes the last day of the bi-annual conference to talk about the company's plans for the next five to ten years. In past years, he has talked up everything from software-defined radios to bio-sensor networks, but this year he focused on Intel's fundamental role as a chip architect.
"We're at the tip of the iceberg in terms of the digitization of information," he explained. As more and more information gets recorded digitally, processors will need to handle terabytes of data and deliver tera bits per second of bandwidth. Just for the record, one terabyte is equal to one trillion bytes.
In order to handle that much data, computers will need to adapt, search through large amounts of data for relevant information and reach a conclusion based on the whole process, Gelsinger said. Performance will increase through shrinking transistors and other innovations, but in order to handle the tera era, an architectural change is necessary.
It's not just processing power that needs to increase in order to reach those goals, he warned. Memory, interconnects and storage will all need to scale alongside processing power in order to realize this vision of the future.
One way Intel is working to enable the tera era is through the use of architectural techniques such as helper threads. Helper threads increase the performance of single-threaded applications by executing as many tasks as possible in parallel on a single processor. This technique becomes even more effective as multi-core processors roll out, Gelsinger said. Multi-core processors integrate more than one CPU onto a single chip.
Another method is the use of software-defined radios to allow users to quickly switch between wireless connections to communicate as effectively as possible, Gelsinger said.
This vision of the tera era won't likely appear before the end of the decade, but it is coming, and the industry needs to prepare, he continued.
Prior to Gelsinger's talk, Intel's general manager Sean Maloney updated the audience on the future of Intel's communications business. It had a tough year in 2003, he said, having to write off $600 million in goodwill after predictions of growth were over-estimated. The flash memory and applications processor business was folded into Maloney's wired and wireless networking group late last year.
Maloney announced a 90-nanometer flash memory product which, according to the company, will be the first NOR flash memory product released at that size. Samples with densities of 64Mbit will be available in April, with volume production starting in the third quarter. The 64Mbit chip will cost $10.26 (£5.46) in quantities of 10,000 units.
Intel also updated its vision for WiMax, the metro-area wireless networking standard that the company thinks will help solve the "last-mile" problem of broadband penetration. Only Japan and South Korea have more than 50 percent of their households using high-speed Net connections, and WiMax could help increase that number, Maloney said.
Wired broadband connections are costly to install and maintain, but WiMax will jump over all those hurdles, he claimed. Consumers should be able to install an antenna on their homes that can access WiMax signals during the first half of 2005, and the technology should be advanced to the point where connections are possible without an antenna by the end of 2005. WiMax products are expected to roll out over the course of 2004.
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