The cutting-edge intelligence research development arm of the government wants to take advantage of the world's semiconductor manufacturing capacity but make sure that US security and intellectual property protection is baked in.
The Intelligence Advanced Research Projects Activity (IARPA) group is looking to fund development of new, advanced chip-making technology under a program it calls Trusted Integrated Chips. TIC would feature what IARPA calls "split-manufacturing," where fabrication of new chips would be divided into Front-End-of-Line (FEOL) manufacturing consisting of transistor layers to be fabricated by offshore foundries and Back-End-of-Line (BEOL) development that would be fabricated by trusted US facilities.
In this approach, the design intention is not disclosed to the FEOL fabricators. "FEOL circuit fabrication to the point of only the first metallisation layer can be used to obfuscate the design and performance of an integrated chip thereby protecting the intellectual property of the designer. Alternately, circuit obfuscation can be realized through a chip integration strategy whereby only partial circuits are fabricated on any single chip but when integrated with other chips or wafers in a US manufacturing or packaging facility, a complete safe and secure circuit or system can be realised," IARPA stated.
"It is desirable for the US academic community and the US industrial base to have open and assured access to obtain the highest performance integrated circuits and systems-on-chips while ensuring that components have been securely fabricated according to design and that intellectual property is protected," IARPA stated.
According to IARPA, the vision of the TIC Program is to ensure that the United States can:
• obtain the highest performance possible in integrated circuits;
• obtain near 100 percent assurance that designs are safe and secure - not compromised with malicious circuitry;
• ensure security of designs, capability, and performance while simultaneously protecting intellectual property; and
• realise secure systems combining advanced CMOS with other high value chips.
IARPA said it wants the TIC program to evaluate a number of split-manufacturing concepts on any of the following design applications:
• Mixed Signal
• RF CMOS
• Josephson Junctions-CMOS
• Other systems integrated with CMOS
IARPA went on to say the five-year program divided into three phases and that development and demonstration of split-manufacturing will start at the 130 nm technology node in Phase 1. It is anticipated that the TIC Program performers will scale the development of their capabilities to the 22 nm node at the end of a five-year period in Phase 3.
The government has selected Sandia National Laboratories to coordinate all FEOL and BEOL processing with Multi-Project Wafer fabrication to be carried out by the University of Southern California/Information Sciences Institute (USC/ISI) using their MOSIS service.
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