Intel's era of tera vision was presented by Pat Gelsinger, Intel's CTO. He singled out TCP/IP offload engines (TOEs) as an example of what would be possible with new chip architecture advances.
Gelsinger said TOEs aren't working because they only fix 22 per cent of the packet I/O problem. Intel analysed what's needed to process a 1KB TCP/IP packet. It took 21,000 clock cycles in a mature Windows stack to do the job. There is a 55 per cent system overhead and 23 per cent of the cycles are spent in memory access time. So we could dedicate a core in a future Intel multicore chip for TCP/IP processing. Gelsinger says "this eliminates huge overhead of O/S scheduling, interrupt processing, user-to-kernel transitions and context switches."
Helper threads are created for the packet to pre-load caches whilst the core is waiting for data. Packet data in the NIC's memory is taken direct to the dedicated core instead of going via the computer system's main memory system. This enables the network stack to be re-optimised. IP processing in Intel's research project was reduced tenfold, down to 2,000 clock cycles. A Xeon CPU system that did "barely a gigabit per second" (of TCP/IP work) scaled "by almost up to ten gigabits per second."
Gelsinger says, "We need (these) non-linear jumps to ... where we will be delivering in every desktop, every laptop, everything that we build, tera-IOPs and FLOPs level of performance."
And meanwhile, in a storage array near you...
What does this portend for storage? If Gelsinger's view is genuine then applications using storage will be working on computers with teraFLOPs of processing power and teraIOPs of bandwidth instead of the low Gbit/sec bandwidth we have today. Let's extrapolate what this means.
Today's GigE and 2Gbit/s Fibre Channel will be scaled up to and beyond TeraE and 1Tbit/s FC bandwidth. The pipes delivering storage data will be radically faster, a thousandfold faster. It means that the drive arrays attached to them have to speed up commensurately so as not to keep everything waiting.
How would you get a 100-drive Symmetrix array or NetApp filer to deliver a thousand more IOs per second?
A marketeer's back-of-the-envelope calculation could say that you get part of it from increasing the number of drives, say by a hundred to a thousand. So your drive array cabinet just got bigger, an awful lot bigger. Even supposing drives could shrink we can't suppose that 1,000 drives tomorrow will occupy the same space as a 100 drives today.
Putting that small problem aside we have only gained a hundredfold speed increase. We need to speed up the storage controllers as well, by a factor of ten so as to achieve our thousandfold increase overall. We'd assume they were running on massively multi-cored chips and give them massive caches. Then the controller will need its cores to do the RAID work and the correlation of what's in the cache(s?) with what's on disk, and where the read/write heads are.
Perhaps we have dedicated read cores and write cores and RAID cores and cache map cores and read/write head operation cores. Perhaps we even have to consider whether to have separate read and write heads inside the disk clamshells.
That's disk, a difficult problem area. But if we think that's hard let's turn to a tape library and ask it to deliver a thousandfold performance improvement. Increasing the number of drives in a library by a factor of a hundred would turn a room-sized library into an office floor-sized library and the robotics would be, well, shall we just say somewhat complex?
Ticklish tera era
Sun has also embraced the multi-core route for its Ultra-Sparc future designs. It would be surprising if IBM were not considering the same kind of chip architecture ideas, not least to keep with Intel's apparently rampaging architectural visions.
Of course, it might not happen. We could see processor performance increase at a more pedestrian pace and Intel fail to obsolete every one of its existing chip-based systems every two years. (Who is running a 486 or Pentium II system now for frontline desktop work?)
Meanwhile the future strategy people inside Seagate, Maxtor, HGST, LSI Logic, Western Digital, StorageTek, and the storage parts of IBM and HP, etc. will be looking over Gelsinger's words. Envelope backs will be used up at a prodigious rate as they ask if Gelsinger's views will come true and what it will mean for the disk platters and tape ribbons that underpin today's whole storage edifice.
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