It's amazing to consider that, with all the upheaval and change that has occurred in the IT world over the past decade, the primary I/O bus architecture for PCs and servers hasn't changed since the early 1990s. Peripheral Component Interconnect (PCI) has been the de facto I/O bus architecture for the better part of 13 years.
Before you start thinking less of some major household names in the IT industry, it should be said first that PCI's longevity is a testament to its effectiveness. It should also be said that earlier attempts to introduce a new and upgraded I/O architecture failed in part because they would have required vendors to rewrite everything from drivers to utilities and management software.
On the horizon is the arrival of PCI Express, a new bus architecture that provides so much performance and scalability that we expect it will be around for a similarly extended period of time. This time around, the designers began their development with backward compatibility as a requirement. By supporting the PCI configuration-space programming model, PCI Express designers removed the dependency on new operating system support. This allows many existing drivers and applications to run on new PCI Express hardware.
Do we really need a new I/O bus architecture now?
PCI did an admirable job providing rock-solid data transport to feed everything from processors to network adapters, to subsystems and graphics cards. But as the speed and capabilities of those surrounding components drastically improved, PCI's maximum 133-MHz speed and its parallel architecture gradually became a bottleneck to system performance.
Today, even budget desktop machines sport 2GHz or 3GHz processors, and data and storage networks commonly run at speeds of 1Gbit/s, 10Gbit/s or even 100Gbit/s. Serial Advanced Technology Attachment hard drives can transmit as much as 1.5Gbit/s to the system bus. Many customers are already "virtualising" servers so multiple logical systems can run on the same physical machine, or they are clustering multiple processors to run a single application.
Each of these advances dramatically increases system performance and can lower costs for the end user. But they also greatly increase the amount of data flowing between peripherals and the system CPU over the system bus. Recognising the limits of PCI, in 2002, a group of vendors including Intel, Hewlett-Packard, IBM and Microsoft unveiled a new I/O architecture called PCI Express (earlier known as "third-generation I/O" or 3GIO).
PCI Express is designed to eliminate many of the limitations of PCI, which is a parallel bus architecture in which multiple adapters must contend for the available bus bandwidth. PCI, which is still the most-used I/O architecture today, is also limited by its data-transfer speed of 133Mbit/s in one direction only. It should be mentioned that an updated and popular version of the PCI bus called PCI-X runs at 133MHz with throughput of up to 1.06Gbit/s. A faster (266MHz) version called PCI-X 2.0 DDR is expected to reach the market later this year with throughput of as much as 2.13Gbit/s. These interim solutions will eventually be replaced by PCI Express, which fully eliminates the parallel architecture; delivers markedly increased performance; and, perhaps most importantly, offers a highly scalable architecture that will support future requirements for many years to come.
PCI Express: What it is and what you get
PCI Express incorporates several fundamental changes compared to PCI and PCI-X. Unlike these older architectures, PCI Express is a point-to-point switching architecture, which creates high-speed, bi-directional links between the CPU and peripherals such as video, network or storage adapters. Each of these links may be made over one or more "lanes" comprising four wires, two for transmitting and two for receiving data.
PCI Express is the new high-performance I/O bus architecture. As a point-to-point switching architecture, PCI Express offers multiple, bi-directional high-speed links between the CPU and peripheral adapters.
In its initial implementation, PCI Express will provide transfer speeds of 250Mbit/s in each direction for each lane. Early PCI Express adapter cards are shipping in configurations of one, four, eight or 16 lanes (called x1, x4, x8 and x16.) Therefore, an x16 PCI Express card can provide as much as 4Gbit/s of throughput in each direction.
For users, this means significantly improved I/O performance and, thus, application performance—especially for demanding applications. Because all traffic routing and resource management is centralized in a single switch, and because of PCI Express' packet-based communication model, the switch can give higher priority to certain types of traffic such as video or audio streams. For systems designers, PCI Express means lower costs and simpler design because each pin has far greater bandwidth.
PCI Express provides for future scalability both in bandwidth (by increasing the number of lanes available), as well as the frequency of the bus. Most server and desktop systems now shipping support PCI Express cards with up to 8 lanes, but the architecture supports as many as 32 lanes. This scalability, along with the expected doubling of the speed of each lane up to 5Gbit/s, should keep PCI Express a viable solution for designers for the foreseeable future.
Lovest Watson is the product manager responsible for PCI Express and blade products at Emulex Corp. in Costa Mesa, Calif.
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