Researchers at the Massachusetts Institute of Technology released research detailing how molecules in chips can self-assemble, potentially reducing manufacturing costs.
The researchers have developed a technique in which polymers automatically fall into place to create an integrated circuit, said Caroline Ross, professor of materials science and engineering at MIT and a researcher behind the technology. The researchers designed a template to cause polymers to spontaneously arrange themselves into useful patterns.
As chips get smaller, they become harder and more expensive to manufacture, Ross said. This technology could allow manufacturers to cut costs involved in etching complex designs on smaller chips.
Chips are manufactured by shining light on silicon or substrates coated with a light-sensitive material called photoresist. The light goes through a template, also called a mask, which projects the detailed pattern on the photoresist, which hardens where it is exposed.
But as chips get smaller, using light to establish smaller structures on chips could be difficult, Ross said. A way to continue shrinking chip features would be to use a beam of electrons to transfer mask patterns to layers of photoresist. Electron beams have to move back and forth across the surface of a chip in parallel lines to establish patterns, which potentially could make the technology more expensive than conventional optical lithography.
However, the MIT researchers used electron beams sparingly to create patterns, as the polymers were adaptable to self-assembly, Ross said. The researchers created blocks on the pattern around which the polymers, polystyrene and polydimethylsiloxane, lined up in a cohesive fashion to create a circuit.
Other researchers involved included Karl Berggren, associate professor of electrical engineering at MIT.
The researchers were the first to use the polymers, Ross said. However, they are not the only ones doing research around self-assembly, and a number of companies including Intel and Micron are researching various materials and designs.
The technology would cut costs in the fabrication of chips, which could help as manufacturers go to smaller scales to make chips, Ross said. Ross said the technique could be used soon, and that companies are interested in the research, but she did not provide names.
Intel today manufactures chips using the 32-nanometer process, the most advanced of its kind. Hard drive manufacturers may be interested in using MIT's technologies as the next generation of hard drives will have tiny magnetic dots at the 10-nm size that store a bit of information.
The researchers are also looking to extend the technique to denser patterns, Ross said. "We want to do something that people would want to be able to use," Ross said.
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