Intel is to launch eight new Pentium 4 processors with a new packaging technique, including its first workstation processors with 64-bit extensions technology, a document posted on Intel's website has revealed.

The forthcoming chips were divulged within a Product Change Notification (PCN) document (#104101-00) that contained details about power management and security enhancements planned for the Pentium 4. Hardware enthusiast site XbitLabs.com first reported on the document.

Intel regularly distributes PCNs to hardware developers and customers to inform them of upcoming changes to existing products or plans to discontinue older products.

Five of the eight new chips will launch alongside the Grantsdale and Alderwood chipsets on 21 June, an Intel spokesman confirmed. Grantsdale and Alderwood are new chipsets that come with support for the PCI Express interconnect technology and DDR2 memory.

Those five Pentium 4 chips will be introduced at clock speeds ranging from 2.8GHz to 3.6GHz and labelled with Intel's new processor numbering system, starting with a 520 label for the 2.8GHz chip and scaling up to a 560 label for the 3.6GHz chip, according to the PCN.

Later in the third quarter, Intel will introduce the first Pentium 4-brand processors with 64-bit extensions to the x86 instruction set, according to the PCN. This technology allows both 32-bit and 64-bit applications to run simultaneously on a system with a 64-bit operating system.

Three Pentium 4 processors with the extensions technology will debut at clock speeds of 3.6GHz, 3.4GHz, and 3.2GHz, according to the PCN. At launch, Intel plans to market these chips only for single-processor servers and workstations, not for desktop PCs, the Intel spokesman said. Even before the launch of the three chips, Intel is expected to introduce its 64-bit extensions technology on its Xeon DP processor for dual-processor servers.

All of the eight new Pentium 4 processors and the two new chipsets will use a different pin packaging technique known as LGA775, according to the PCN. This means Intel will use the Land Grid Array packaging technique with 775 pins on each processor.

The pins on a processor connect the chip to the rest of the motherboard. Intel's current Pentium 4 processors use 478 pins. An increase in the number of pins allows Intel to improve the quality of the electrical signals within the chip and get more power into the Prescott core.

Intel shipped the early versions of the Prescott Pentium 4 processors with the extensions technology disabled, executives have said. In order to enable the extensions technology as well as future enhancements such as a faster front-side bus and higher clock frequencies, Intel needed to implement the new packaging technique, said Kevin Krewell, editor-in-chief of the Microprocessor Report, in San Jose, California.

The PCN also confirmed Intel's intentions to incorporate power management and security features into forthcoming Pentium 4 processors as part of a new stepping. A stepping is an enhancement to an existing product that chip companies use to make changes without having to test and qualify a new piece of silicon. Most companies release several steppings to original core designs to correct minor flaws or enhance certain features.

Prescott is Intel's first 90-nanometer processor, and its power consumption has raised eyebrows among analysts and PC industry observers. The first Prescott chips launched in February consume between 90 and 115 watts of power, more than the previous generation of its Pentium 4 chips.

In order to ensure the chips will work at clock speeds faster than the 3.4GHz currently available, Intel plans to introduce new power management features, according to the PCN.

Intel COO Paul Otellini briefly discussed an upcoming power management technology called AAC during the company's analyst meeting in May, but didn't provide specifics. Intel already uses a technique called SpeedStep to manage power in mobile processors, and AAC is a similar technology, the Intel spokesman said.

The company will implement support for the NX bit that prevents buffer overflow attacks in the new stepping, according to the PCN. In May, Otellini confirmed Intel's plans to enable NX support in future Prescott processors.