Fujitsu has previewed a quad-core Sparc processor that it plans to release for high-end Unix servers in 2008.

The Sparc64 VI+, codenamed Jupiter, will incorporate four separate processing cores on a single chip, said Takumi Maruyama, manager of enterprise server development at Fujitsu. It will run at up to 2.7GHz and consume somewhere in the neighborhood of 120 watts of power at maximum.

Fujitsu still has yet to ship the Sparc64 VI+ processor's predecessor, codenamed Olympus, or the Sparc64 VI, but has reached a crucial milestone by finalising its design.

The dual-core Sparc64 VI processor lays the groundwork for the quad-core Sparc64 VI+. Each core on the processors can handle two software threads at the same time, allowing the Sparc64 VI to handle four independent threads and the Sparc64 VI+ to handle eight.

Both processors will use the same bus technology for connecting the processor to memory, Maruyama said. In the multi-core processor era, keeping the processors fed with data funneled through a high-speed connection to memory is essential to get the most out of it.

Even though the four cores on the Sparc64 VI+ will share a single connection to memory, the bandwidth of that bus is sufficient to keep the cores running at maximum capacity, Maruyama said.

Multiple core chips are ideal for multithreaded software applications, which are becoming more and more prevalent. But Fujitsu's chip designers are still concerned with ensuring that single-threaded applications continue to benefit from new technology, Maruyama said.

The company is using a technique called VMT, or virtual multi-threading, to maximize the performance of software threads moving through the chip. If one thread needs information that it can't find in the on-chip cache memory, and therefore needs to request that data from the main memory, the Sparc64 VI processor can quickly switch to another thread that has all the data it needs, Maruyama said.

This prevents the processor from idling while waiting for the data from main memory, and should deliver a 20 percent improvement in performance over older Sparc64 chips without this technology, he said.