The European Commission has now joined the worldwide race to perfect the next generation of chip production and reduce the largest component from an existing state-of-the-art 90 nanometres to 45 nanometres and smaller.

With such a production process, chips would be smaller, more powerful and consume less energy - enabling those with the technology to seize control of a multi-billion-pound market.

The new collaborative research project, called NANOCMOS, hopes to pioneer changes in materials, processes, device architectures and interconnections to push the limits of semiconductor performance and density. Researchers will focus on next-generation CMOS technology, beginning with 45nm chip production and extending to 32 and 22-nanometer processes.

However, the EC is not alone in its desire to perfect the 45nm production process. Last month, Sony and Toshiba announced they would spend £50 million trying to achieve just that. Both companies are working with IBM at producing 65nm chips but made it clear that they are going for the 45nm prize on their own.

IBM of course has something to say about this. It is already working toward 45nm, and Samsung has been the most recent company to provide it with an unspecified sum to get a slice of the action, joining Chartered Semiconductor and Infineon who put their stake in last August.

Plus, of course, chip manufacturers Intel and AMD - the most experienced at this technology - are each separately attempting to get to the end tape before everyone else. Intel has already announced 65nm technology, due to be commercially available next year.

CMOS technology - the most widely used integrated circuit design - is found in almost every electronic product, ranging from handheld devices to mainframe computers.

The Commission has agreed to provide seed capital of €24 million (£16m) for the research project, with participating chip makers and research institutes expected to match it.

In the first phase of the project, expected to last 27 months, researchers will demonstrate the feasibility of 45-nanometer CMOS logic technology, as well as begin research activities on 32 and 22-nanometer CMOS technologies. The second phase, starting in 2006, will then demonstrate the feasibility of the 32 and 22-nanometer chip production processes. The goal is to develop such chips as early as 2007.

Among the project's backers are Phillips, STMicroelectronics, Infineon and a range of scientific centres and research institutes - 12 enterprises in total.

In addition to the NANOCMOS project, the Commission has agreed to sponsor a "network of excellence" called SINANO. The aim of the networking initiative is to bring together all Europe research centers that could contribute, in some way, to the development of silicon-based devices on the scale of one to 40 nanometers.