Intel has been spreading a TOEs are not needed message at its Intel Developer Forum. Use I/O AT instead and have TCP/IP stack procesing carried out efficiently by an Intel CPU-chipset-NIC combination. We doubted that, after reading a couple of Intel papers, this would work for serious networked (iSCSI) environments. Comments coming in to Techworld suggest that this reading of the situation is right.
Here is Kianoosh Naghshineh, CEO of Chelsio Communications: "Intel is understandably adopting the same approach that it did with MMX instructions and graphics, attempting to slow down the adoption of any offload technology so as to sell more CPUs. In the end, it created the opportunity for nVidia and ATi to become a franchise, and this time for Chelsio to follow the same path."
What he is seeing is that the attempt to negate the need for graphics cards, aka graphics offload engines or GOEs, failed. CPUs can't handle complex graphics AND run application code as well. It's generally perceived now that CPUs need to have graphics processing offloaded into an additional graphics card.
Naghshineh calculates that once the TOE silicon is priced at commodity levels it will, as a matter of course, take over the general NIC market: "once the offload silicon is cheap enough to provide a zero premium for offload, it will encompass the NIC market. Given the Microsoft support for offload, mass adoption of offload technology by later this year is the natural conclusion, regardless of Intel’s position."
Another driver of this effect will be the adoption of 10 gig technology: "By all accounts the explosion of 10G technology is expected to be in the last quarter of this year. Once the offload silicons are there to address 10G, they will automatically come back to pick up 1G market."
Naghshineh also sees Intel's need to compete against AMD as being one of the causes for Intel's I/O AT initiatives.: "Finally, the intel proposal for technology is advocating buying intel’s chipsets as well since it houses part of the technology. The other chipset vendors or AMD are most likely not on board with that."
Hamish Macarthur of Macarthur Stroud International says Intel, in its two paper, "appears (to be) talking about enhanced direct memory access (DMA). We see that most iSCSI implementations are using standard NICs and therefore (making) little use of offload engines such as TOEs. The performance achieved is acceptable to users because they are implementing such solutions in lower duty cycle environments. For high performance networks (Fibre Channel SANs), we have HBAs providing the offload capability because larger blocks are being handled."
So low rate networked iSCSI storage access doesn't need TOEs but higher duty cycle storage access will. He concurs that server-client communications don't need TOE support, also that Intel probably is talking about server-client communications: "I believe Intel is talking about server architectures and is taking new functionality on board, i.e. improved DMA, to improve latency and harness this with multithreading; then there is little benefit to go with an offload solution. This arises because in high volume transaction environments they are referring to, the transactions are relatively small and are typically handled with shorter (1K) packets."
"In the second paper about I/O AT, Intel is talking about a network I/O accelerator and a storage I/O accelerator. The functions of a TOE are less than an HBA which is doing what Intel is addressing; however, it makes no reference to such a device. I know that HBAs tend to be Fibre Channel, but there is no reason what they are not also applied in Ethernet environment. This development, perhaps, indicates why the HBA suppliers are not looking in such a positive way to introduce an iSCSI HBAs. This will also emphasise where iSCSI networks play and where Fibre Channel networks play, as above."
"In the I/O domain, there are also interesting developments such as Emulex’s Switch on a Chip which is re-architecting storage access from the storage controller."
Macarthur thinks that Intel may have the wrong end of the stick also, and in two ways: "In conclusion, it appears that Intel is providing its own network and storage offload engines to speed up system performance. But these are now tightly coupled to the CPU and memory, and, as a result, accelerators such as TOEs are no longer relevant. But the role of these were in question anyway because the iSCSI implementations appear to work well in low duty cycle environments with standard NICs."
So TOEs are not needed in low duty cycle iSCSI environments, and, logically, Intel's IO/ AT isn't needed either.
But TOEs do seem to be needed in high duty cycle iSCSI environments and Intel's I/O AT isn't needed there because it doesn't provide as much benefit as a TOE does. The word from Chelsio and Macarthur Stroud International is that, for serious networked IP storage, you do need to be on your TOEs.
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